Communication bus system

ABSTRACT

The bus controller of a bus system supports isochronous messages and non-isochronous messages for which the bus system does and does not support a guaranteed transceiving capacity per time-frame respectively. The system has a first and second memory section for exchange of data from the isochronous messages between a processor and the bus controller. The bus controller has access priority over the processor in alternating first and second ones of the time frames. The bus controller transfers data from isochronous messages between the bus medium and the first and second memory section in the first and second ones of the time frames respectively. The processor has access priority to the first and second memory section over the bus controller in the second and first ones of the time frames respectively. The system contains a third memory section for exchange of data from the non-isochronous messages, a relative access priority of the processor and bus-controller to the third memory section being unchanged in all time frames.

The invention relates to a communication bus system like a USB system.

Nowadays the USB (Universal Serial Bus) is frequently used in PC's(Personal Computers). The USB provides for transfer of data over a busmedium that is made up of USB cables. A PC serves as USB host and isconnected on one side to these cables. USB devices are connected to theother side of the cables, possibly via hubs. In the PC, the USBfunctionality is implemented in a host controller HC which communicateswith the system processor and other system resources via an internalsystem bus. Normally, the host controller and the processor communicatevia a memory. The host controller writes data received from the busmedium into a memory or reads data that has to be transmitted from thememory. The processor reads or writes this data into the memory.Obviously, the host controller cannot transmit data before the processorhas generated this data and written it into memory. Similarly the hostprocessor will have to process received data quickly enough to ensurethat the memory does not overflow with unprocessed received data.

USB provides for transfer of isochronous and non-isochronous messagesover the bus medium. Isochronous messages concern for example real timedata, such as voice or audio signals and their transfer has to meet realtime constraints. A guaranteed transfer bandwidth has to be available.This is implemented in successive time frames. The host controllerensures that a guaranteed amount of data can be transferred inisochronous packets in each time frame. That is, in case the hostcontroller has to transmit isochronous messages, the host controller hasto have the data available in time (usually in a memory), or the hostcontroller has to have memory available to store incoming data in caseof received isochronous messages. Transmission and reception ofnon-isochronous messages can be delayed until resources becomeavailable.

Conventionally, the host controller is made master of the system bus toensure that it has access to memory in time when it needs to write orread data of isochronous messages. This is no problem if the processorand the bus are very fast and powerful, which is usually the case inPC's. However, in case of less powerful processors, such as for examplein low cost hand held devices like mobile telephones, palmtop PC's etc.that can operate as a USB host, the host controller may impose too higha load on the internal bus, leaving to little time for the processor toprocess the data, or to perform other (not bus related) functions,needed in a mobile telephone for example.

Amongst others, it is an object of the invention to provide for anarchitecture for a processing system that can handle isochronous messageas well as non-isochronous messages in such a way that not too littletime is left for processing by the processor.

The communication bus system according to the invention is set forth inclaim 1. According to the invention the system comprises differentmemory sections for isochronous and non-isochronous messages. The hostcontroller and the processor can access different ones of the memorysections in parallel without hindering each other. Arbitration is neededif they attempt to access the same memory section in parallel. To ensureunhindered transfer of isochronous messages at least two memory sectionsare provided for isochronous messages. In successive time frames thehost controller is given highest priority access to a alternating onesof these memory sections. The processor is given highest priority accessto the other (or other ones) of these memory sections in each timeframe.

Highest priority access may be ensured in many ways, for example bymeans of exclusive access, denying any access to one of the hostcontroller or processor when it is indicated that the other one has highpriority access. Alternatively, an arbitration mechanism may be usedthat arbitrates each memory transaction individually.

A further memory section is provided for the non-isochronous messages.Both the host controller and the processor have access to this furthermemory. Their relative access priority to this memory does not changefrom one time-frame to another. By way of example priority is determinedby means of arbitration between the host controller and the processor todetermine who gets access to this memory section. By providing aseparate memory section for non-isochronous messages, the special memorysections for isochronous messages can be kept small.

In an embodiment the system is interrupt based, the host controllersending interrupts to the processor when it has finished transfer ofmessages for a time-frame. Thus, the processor is enabled to startaccess to the first or second memory section after the host controllerhas completed transfer of messages, even if the time-frame is not yetfinished.

In a further embodiment isochronous messages are transferred first andseparate interrupts are generated upon completion of transfer of theisochronous messages and upon completion of transfer of thenon-isochronous messages. Thus, the processor is enabled to start accessto the first or second memory section even during the time-frame inwhich the host processor has highest access priority to that memorysection after completion of transfer of isochronous messages, but beforecompletion of transfer of all messages.

These and other advantageous aspects of the bus system according to theinvention will be described in more detail using the following figures.

FIG. 1 shows a bus system

FIG. 2 shows a sequence of time frames

FIG. 3 shows a transaction descriptor

FIG. 1 shows a USB system. The system contains a USB host 1, USBconnections 17 a,b and USB devices 18 a,b. The USB host 1 contains aprocessor 10, a bus control unit 12, a common memory 14, all connectedvia an internal bus 16. The bus control unit 12 contains a hostcontroller 120, a first memory 122 a, a second memory 122 b, a firstaccess control unit 124 a and a second access control unit 124 b. Thefirst and second memory 122 a,b are coupled to the internal bus 16 viafirst and second access control unit 124 a,b respectively, via a firstaccess port of each of these access control units 124 a,b.

The host controller 120 is connected to the USB connections 17 a,b.Furthermore, the host controller 120 is connected to the internal bus16, to a control input of the first and second access control unit 124a,b and to the first and second memory 122 a,b via second ports of thefirst and second access control unit 124 a,b. The host controller 120has an interrupt line 15 coupled to processor 10.

In operation the system transfers messages to and from USB devices 18a,b via USB connections 17 a,b. Data from the messages is produced orconsumed by processor 10. In case data has to be sent to a USB device 18a,b processor 10 writes this data into one of the common memory 14 orfirst or second memory 122 a,b (directly or using DMA). Host controller120 reads this data from the relevant memory 14, 122 a,b, encapsulatesthe data in a message and sends the message to an addressed device 18a,b via a USB connection 17 a,b. Similarly, when a message has to bereceived from a USB device 18 a,b, host controller 120 writes data fromeach message in one of the common memory 14 or the first and secondmemory 122 a,b. In this case processor 10 subsequently reads this datafrom the relevant memory 14, 122 a,b (directly or using DMA).

Access to the common memory 14 via internal bus is conventional, usingfor example an arbiter (not shown), or under control of processor 10.Access to the first and second memory 122 a,b is controlled by accesscontrol units 124 a,b. Both access control units 124 a,b have a firstand a second mode of operation. In the first mode the access controlunit 124 a,b gives access to the corresponding memory 122 a,b via theinternal bus, via the first port of access control unit 124 a,b. Thismay be normal address mapped access. In the second mode the accesscontrol unit 124 a,b gives host controller 120 access to thecorresponding memory 122 a,b. The mode is selected by host controller120 via the control inputs of the access control units 124 a,b.

Host controller 120 operates in successive time-frames. In each timeframe host controller 120 reserves a certain amount of time fortransmission of isochronous messages. Isochronous messages serve toguarantee that real time signals can be transmitted on time via USBconnections 17 a,b. When a program executing in processor 10 wants totransmit a real time signal, it determines how much transmission timewill be needed per frame for this signal and requests that hostcontroller 120 reserves that amount of time in each time frame. If nottoo much time has already been reserved host controller 120 grants therequest (if not, the program cannot start the signal). In this way it isensured that sufficient data can be transmitted in each frame forsignals for which host controller 120 has granted a request.

FIG. 2 illustrates operation of the system as a function of time “t”.Time is divided in successive time-frames (shown starting at timesT1–4). In each time frame a time interval 21 a–d occurs in whichisochronous messages are transmitted, followed by a time interval 23 a–din which other, non-isochronous messages are transmitted. The length ofthese time intervals 21 a–d, 23 a–d may vary from frame to frame,depending on the actual amount of data that has to be transferred. Asshown, some of the time-frame may be left unused for transmission. Thisis not necessarily so; it also depends on the actual amount of data thatneeds to be transferred.

FIG. 2 shows, in addition, four lines representing, successively fromtop to bottom access to the first memory 122 a by the host controller120, access to the first memory 122 a by the processor 10, access to thesecond memory 122 b by the host controller 120, access to the secondmemory 122 b by the processor 10. Right of access is shown by a solidline, lack of that right is shown by dashed lines.

In successive time frames host controller 120 seizes access to alternateones of the first and second memory 122 a,b, for the duration of thetime interval 21 a–d for transfer of data from isochronous messages.That is, in the time intervals 21 a,c of the odd (first and third)time-frames (starting with T1, T3) host controller 120 seizes access tothe first memory 122 a and in the time intervals 21 b,d of the even(second and fourth) time frames (starting with T2, T4) host controller120 seizes control of the second memory 122 b. During the time interval21 a–d for transfer of isochronous messages host controller 120 writesor reads data to or from the memory 122 a,b to which it has seizedcontrol. This data is taken from received isochronous messages or putinto transmitted isochronous messages.

Processor 10 has access to each of the first and second memory 122 a,bvia internal bus 16 when host controller 120 has not seized control ofthe relevant memory 122 a,b. Thus, processor 10 at least has access toeach particular memory 122 a,b during the time-frame before the timeframe in which host controller reads data from that memory 122 a,b foruse in isochronous messages and in the time frame after the time-framein which host controller 120 writes data from isochronous messages intothat memory. This gives processor 10 the opportunity to write or readthat data in one time frame and it gives host controller 120 theopportunity to receive and transmit isochronous messages without delayin another time frame.

At the time I1–I4 when host controller 120 has finished receiving ortransmitting isochronous messages in a time-frame, host controller 120relinquishes access to the first or second memory 122 a,b used for thatreceiving or transmitting. Thus, processor 10 gets the opportunity inthe remainder of the time frame to write or read that memory 122 a,b. Ofcourse, this opportunity continues into the next time frame, since hostcontroller 120 will read or write from the other memory 122 a,b in thattime frame. In total therefore processor 10 gets an interval of morethan a whole time-frame to read or write data for isochronoustransmission.

In FIG. 2 for example, host controller 120 seizes access to the firstmemory 122 a during the first time-frame in interval 20 from the starttime T1 of the time frame to the time I1 at the end of isochronousmessage transfer. After that time I1 host controller 120 relinquishesaccess in a time interval (shown as a dashed line 20 a) until the startT3 of the third time frame. From time I1 to the start time T3 of thethird time-frame (interval of solid line 22) processor 10 has theopportunity to access the first memory 122 a. Similarly host controller120 seizes access to the second memory 122 b during the secondtime-frame in interval 24 from the start time T2 of the time frame tothe time I2 at the end of isochronous message transfer. After that timeI2 host controller 120 relinquishes access in a time interval until thestart T4 of the fourth time frame. From time I2 to the start time T4 ofthe fourth time-frame (interval 26) processor 10 has the opportunity toaccess the second memory 122 a.

After the time I1–4 of completion of transfer of isochronous messagesnon-isochronous messages are transferred, using data from common memory14, until a time I5–8 when no data is left or the time-frame ends. Hostcontroller 120 normally contends with processor 10 for access to theinternal bus 16 to access common memory 14. Therefore, if hostcontroller 120 loses access to processor 10, transfer of data fornon-isochronous messages may have to be delayed.

Host controller 120 generates two interrupts for processor 10 per timeframe, a first one at the time I1–4 when isochronous message transferhas been completed and a second one at the time I5–8 whennon-isochronous transfer has been completed. The first interrupt signalsthat processor 10 gets back the opportunity to access that one of thefirst and second memory 122 a,b that the host controller 120 has usedfor isochronous data transfer in the current time frame. This enablesthe processor 10 to read or write data to that memory 122 a,b for therest of that time frame and for the next time frame. Thus the processor10 gets maximum opportunity to transfer data to or from the memory 122a,b.

The second interrupt (at time I5–8) signals that host controller 120 hascompleted non-isochronous data transfer in the time frame. This enablesprocessor 10 to adapt the data transfer to time intervals that lead tominimum interference with host controller 120.

FIG. 3 shows the format of a transaction descriptor for USB messagetransfer. Processor 10 loads data descriptors with this format into thememories 122 a,b, 14 to signal the need for message transfer to hostcontroller 120. The descriptor is followed by memory space for the datathat is transferred. It will be noted that the descriptor is notnecessarily limited to one message (also called “packet” in USB): thedescriptor describes a block of data that host controller 120 may sendor receive in one or more message. The meaning of the various fields inthe descriptor and whether they are read or written by host controller(column “Access”) is illustrated in the following table.

TABLE Name Access Description ISO R indicates type of message Speed Rindicates speed of message DirectionPID R direction of data flow: in/outor setup (two-way) EndpointNumber R USB address of destination endpointwithin function FunctionAddress R USB address of destination functionToggle R/W Toggled after each successful transfer MaximumPacketSize Rmaximum number of bytes per message TotalBytes R Total number of bytesdescribed by descriptor Active R/W Enable bit for hostcontroller/completion bit for processor Error R/W error indicator oftransfer ErrorCode R/W type of error ActualBytes R/W number of bytestransferred

Host controller 120 reads information from the descriptor, transmits orreceives data according to the descriptor and writes back statusinformation into the descriptor. Depending on whether a USB message issent or received host controller 120 reads or writes the data followingthe descriptor.

Preferably, host controller 120 visits the descriptors stored in memory122 a,b sequentially during each frame and transmits or receives amessage for each descriptor for which the “Active” bit is set. When alldata for the descriptor has been transferred, host controller 120 clearsthe “Active” bit. When the host controller has transferred messages forall descriptors in a time frame and there is still time left, hostcontroller 120 visits the descriptors again and transfers messages forthose descriptors where the “Active” bit has not yet been cleared. Thus,a maximum amount of data can be transferred in a time-frame.

It will be understood that the embodiment described thus far is but oneof the embodiments of the invention. For example, without deviating fromthe invention data for one or more non-isochronous message may be storedin the first or second memory 122 a,b in addition to the data for theisochronous messages if there is room for this data. Of course this maylimit transfer of this data to even or odd time frames if hostcontroller 120 does not manage to transfer all data in one time frame.In another example, host controller 120 may have an additional memoryfor buffering the data that is actually transferred, this data beingfetched from memory 122 a,b, 14 or stored in the memory 122 a,b, 14before or after completion of the message respectively. The processor 10may have a cache memory to store some of the data temporarily, the datafrom the cache being transferred when this is allowed by the hostcontroller 120. DMA may be used to transfer data to and from thememories 122 a,b, 14. Instead of bus addressed memory 122 a,b specialfunction registers in the processor may be used to access one or more ofthe memories.

1. A communication bus system comprising: a bus medium (16); a buscontroller (120) that is arranged to transmit and/or receive messagesvia the bus medium (16) in successive time frames, the bus controller(120) supporting isochronous messages and non-isochronous messages forwhich the bus system does and does not support a guaranteed transceivingcapacity per time-frame respectively; a processor (10); a first andsecond memory section (122 a,b) for exchange of data from theisochronous messages between the processor (10) and the bus controller(120), the bus system being arranged to give the bus controller (120)access priority over the processor (10) in first and second ones of thetime frames respectively, the first and second ones of the time-framesalternating with one another, the bus controller (120) transferring datafrom isochronous messages between the bus medium (16) and the first andsecond memory section (122 a,b) in the first and second ones of the timeframes respectively, the processor (10) having access priority to thefirst and second memory section (122 a, b) over the bus controller (120)in the second and first ones of the time frames respectively; a thirdmemory section (14) for exchange of data from the non-isochronousmessages, a relative access priority of the processor (10) andbus-controller (120) to the third memory section (14) being unchanged inall time frames.
 2. A communication bus system according to claim 1,wherein the bus controller (120) has an interrupt output and theprocessor (10) has an interrupt input coupled to the interrupt output,the bus controller (120) being arranged to send an interrupt to theprocessor (10) upon completion of data transfer using the first andsecond memory section (122 a,b) in the first and second time framesrespectively.
 3. A communication bus system according to claim 2,wherein the bus controller (120) is arranged to transfer the databetween the bus medium (16) and the first or second memory section (122a,b) in each time frame before transferring data between the bus medium(16) and the third memory section (14), the bus controller (160) beingarranged to send a further interrupt upon completion of data transferusing the third memory section (14) in each time frame.
 4. Acommunication bus system according to claim 3, wherein the processor(10) is programmed to start reading or writing the data in the first andsecond memory section (122 a,b) in response to the interrupt in thefirst and second time frame respectively.
 5. A communication businterface circuit (12) comprising: an interface for connecting a busmedium (16); a bus controller (120) that is arranged to transmit and/orreceive messages via the interface in successive time frames, the buscontroller (120) supporting isochronous messages and non-isochronousmessages for which the bus interface circuit does and does not support aguaranteed transceiving capacity per time-frame respectively, aninterface for a processor (10); a first and second memory section (122a,b) for exchange of data from the isochronous messages between theprocessor (10) and the bus controller (120), the bus interface circuit(12) being arranged to give the bus controller (120) access priorityover the processor (10) in first and second ones of the time framesrespectively, the first and second ones of the time frames alternatingwith one another, the bus controller (120) transferring data fromisochronous messages between the interface for the bus medium (16) andthe first and second memory section (122 a,b) in the first and secondones of the time frames respectively, the interface for the processorhaving access priority to the first and second memory section (122 a,b)over the bus controller (120) in the second and first ones of the timeframes respectively; an interface to a third memory section (14) forexchange of data from the non-isochronous messages, a relative accesspriority of the interface for the processor (10) and bus-controller(120) to the third memory section being unchanged in all time frames.